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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
68030/040 PECL-TTL Clock Driver
The MC10H/100H642 generates the necessary clocks for the 68030, 68040 and similar microprocessors. It is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part-to-part skew, within-part skew and also duty cycle skew. The user has a choice of using either TTL or PECL (ECL referenced to +5.0V) for the input clock. TTL clocks are typically used in present MPU systems. However, as clock speeds increase to 50MHz and beyond, the inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The H642 also uses differential PECL internally to achieve its superior skew characteristic. The H642 includes divide-by-two and divide-by-four stages, both to achieve the necessary duty cycle skew and to generate MPU clocks as required. A typical 50MHz processor application would use an input clock running at 100MHz, thus obtaining output clocks at 50MHz and 25MHz (see Logic Diagram). The 10H version is compatible with MECL 10HTM ECL logic levels, while the 100H version is compatible with 100K levels (referenced to +5.0V).
MC10H642 MC100H642
68030/040 PECL-TTL CLOCK DRIVER
26 4 5
11
* * * * * *
Generates Clocks for 68030/040 Meets 030/040 Skew Requirements TTL or PECL Input Clock Extra TTL and PECL Power/Ground Pins Asynchronous Reset Single +5.0V Supply
FN SUFFIX PLASTIC PACKAGE CASE 776-02
Function Reset(R): Select(SEL):
LOW on RESET forces all Q outputs LOW. LOW selects the ECL input source (DE/DE). HIGH selects the TTL input source (DT). The H642 also contains circuitry to force a stable input state of the ECL differential input pair, should both sides be left open. In this Case, the DE side of the input is pulled LOW, and DE goes HIGH. Power Up: The device is designed to have positive edges of the /2 and /4 outputs synchronized at Power Up.
VT 25 Q2 GT GT Q3 VT VT Q4 26 27 28 1 2 3 4 5 Q5 6 GT 7 GT 8 Q6 9 Q7 10 VT 11 SEL VT 24 Q1 23 GT 22 GT 21 Q0 20 VT 19 18 17 16 VBB DE DE VE R GE DT
Pinout: 28-Lead PLCC (Top View)
15 14 13 12
9/96
(c) Motorola, Inc. 1996
2-1
REV 4
MC10H642 MC100H642
LOGIC DIAGRAM
TTL Outputs Q7 Q6 TTL/ECL Clock Inputs VBB DE DE DT Q3 SEL Q2 /4 Q5 Q4
MUX
TTL Control Inputs
/2
Q1 Q0
R
PIN NAMES
Pin 81 82 83 84 85 86 87 88 89 10 11 12 13 14 **Divide by 2 **Divide by 4 Symbol Q3 VT VT Q4 Q5 GT GT Q6 Q7 VT SEL DT GE R Description Signal Output (TTL)** TTL VCC (+5.0V) TTL VCC (+5.0V) Signal Output (TTL)** Signal Output (TTL)** TTL Ground (0V) TTL Ground (0V) Signal Output (TTL)** Signal Output (TTL)** TTL VCC (+5.0V) Input Select (TTL) TTL Signal Input ECL Ground (0V) Reset (TTL) Pin 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol VE DE DE VBB VT Q0 GT GT Q1 VT VT Q2 GT GT Description ECL VCC (+5.0V) ECL Signal Input (Non-Inverting) ECL Signal Input (Inverting) VBB Reference Output TTL VCC (+5.0V) Signal Output (TTL)* TTL Ground (0V) TTL Ground (0V) Signal Output (TTL)* TTL VCC (+5.0V) TTL VCC (+5.0V) Signal Output (TTL)** TTL Ground (0V) TTL Ground (0V)
MOTOROLA
2-2
MECL Data DL122 -- Rev 6
MC10H642 MC100H642
AC CHARACTERISTICS (VT = VE = 5.0V 5%)
TA = 0C Symbol tPLH Characteristic Propagation Delay D to Output Part-to-Part Skew Within-Device Skew Propagation Delay D to Output Part-to-Part Skew Within-Device Skew Propagation Delay R to Output Output Rise/Fall Time 0.8 V to 2.0 V Maximum Input Frequency Reset Pulse Width Reset Recovery Time All Outputs All Outputs 100 1.5 1.25 4.3 Q0, Q1 C ECL C TTL All Outputs 4.30 4.30 Q2-Q7 C ECL C TTL Min 4.70 4.70 Max 5.70 5.70 1.0 0.5 5.30 5.30 2.0 1.0 6.3 2.5 2.5 100 1.5 1.25 4.0 4.50 4.50 TA = 25C Min 4.75 4.75 Max 5.75 5.75 1.0 0.5 5.50 5.50 2.0 1.0 6.0 2.5 2.5 100 1.5 1.25 4.5 4.25 4.25 TA = 85C Min 4.60 4.50 Max 5.60 5.50 1.0 0.5 5.25 5.25 2.0 1.0 6.5 2.5 2.5 ns ns ns ns MHz ns ns CL = 25pF CL = 25pF CL = 25pF CL = 25pF CL = 25pF ns ns ns CL = 25pF Unit ns Condition CL = 25pF
tskpp tskwd* tPLH
tskpp tskwd tPD tR tF fMAX** RPW RRT
* Within-Device Skew defined as identical transactions on similar paths through a device. ** NOTE: MAX Frequency is 135MHz.
10H PECL CHARACTERISTICS (VT = VE = 5.0V 5%)
TA = 0C Symbol IIH IIL Characteristic Input HIGH Current Input LOW Current * NOTE VIH VIL Input HIGH Voltage Input LOW Voltage * NOTE VBB Output Reference Voltage 3.62 3.73 3.65 3.75 3.69 3.81 V 3.83 3.05 4.16 3.52 3.87 3.05 4.19 3.52 3.94 3.05 4.28 3.555 V VEE = 5.0V Min 0.5 Max 225 0.5 TA = 25C Min Max 175 0.5 TA = 85C Min Max 175 Unit A Condition
100H PECL CHARACTERISTICS (VT = VE = 5.0V 5%)
TA = 0C Symbol IIH IIL Characteristic Input HIGH Current Input LOW Current * NOTE VIH VIL Input HIGH Voltage Input LOW Voltage * NOTE VBB Output Reference Voltage 3.620 3.740 3.620 3.740 3.620 3.740 V 3.835 3.190 4.120 3.525 3.835 3.190 4.120 3.525 3.835 3.190 4.120 3.525 V VEE = 5.0V Min 0.5 Max 225 0.5 TA = 25C Min Max 175 0.5 TA = 85C Min Max 175 Unit A Condition
*NOTE: PECL LEVELS are referenced to VCC and will vary 1:1 with the power supply. The VALUES shown are for VCC = 5.0V.
MECL Data DL122 -- Rev 6
2-3
MOTOROLA
MC10H642 MC100H642
10H/100H DC CHARACTERISTICS (VT = VE = 5.0V 5%)
TA = 0C Symbol IEE ICCH ICCL Characteristic Power Supply Current PECL TTL Min Max 57 30 30 TA = 25C Min Max 57 30 30 TA = 85C Min Max 57 30 30 Unit mA mA mA Condition VE Pin Total All VT Pins
10H/100H TTL DC CHARACTERISTICS (VT = VE = 5.0V 5%)
TA = 0C Symbol VIH VIL IIH IIL VOH VOL VIK IOS Characteristic Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Input Clamp Voltage Output Short Circuit Current -100 2.5 2.0 0.5 -1.2 -225 -100 Min 2.0 0.8 20 100 -0.6 2.5 2.0 0.5 -1.2 -225 -100 Max TA = 25C Min 2.0 0.8 20 100 -0.6 2.5 2.0 0.5 -1.2 -225 Max TA = 85C Min 2.0 0.8 20 100 -0.6 A mA V V V mA VIN = 2.7V VIN = 7.0V VIN = 0.5V IOH = -3.0mA IOH = -15mA IOL = 24mA IIN = -18mA VOUT = 0V Max Unit V Condition
10/100H642 DUTY CYCLE CONTROL
To maintain a duty cycle of 5% at 50 MHz, limit the load capacitance and/or power supply variation as shown in Figures 1 and 2. For a 2.5% duty cycle limit, see Figures 3 and 4. Figures 5 and 6 show duty cycle variation with temperature. Figure 7 shows typical TPD versus load. Figure 8 shows reset recovery time. Figure 9 shows output states after power up. Best duty cycle control is obtained with a single P load and minimum line length.
MOTOROLA
2-4
MECL Data DL122 -- Rev 6
MC10H642 MC100H642
11 11 POSITIVE PULSE WIDTH (ns) NEGATIVE PULSE WIDTH (ns)
10
4.75 5.00 5.25
10
4.75 5.00 5.25
9 9 0 0 10 20 30 40 50 60 CAPACITIVE LOAD (pF) 10 20 30 40 50 CAPACITIVE LOAD (pF) 60
Figure 1. MC10H642 Positive PW versus Load @ 5% VCC, TA = 25C
Figure 2. MC10H642 Negative PW versus Load @ 5% VCC, TA = 25C
10.8 10.6 10.4 10.2 10.0 9.8 9.6 9.4 4.875 5.00 5.125
10.6 NEGATIVE PULSE WIDTH (ns) 10.4 POSITIVE PULSE WIDTH (ns) 10.2 10.0 9.8 9.6 9.4 9.2 0 10 20 30 40 CAPACITIVE LOAD (pF) 50 60 4.875 5.00 5.125
0
10
20
30
40
50
60
CAPACITIVE LOAD (pF)
Figure 3. MC10H642 Positive PW versus Load @ 2.5% VCC, TA = 25C
Figure 4. MC10H642 Negative PW versus Load @ 2.5% VCC, TA = 25C
10.4 POSITIVE PULSE WIDTH (ns) NEGATIVE PULSE WIDTH (ns) 10.2 10.0 9.8 9.6 9.4 0 20 40 60 TEMPERATURE (C) 80 100 0 pF 25 pF 50 pF
10.5 10.3 10.1 9.9 9.7 9.5 0 20 40 60 80 100 0 pF 25 pF 50 pF
TEMPERATURE (C)
Figure 5. MC10H642 Positive PW versus Temperature, VCC = 5.0V
Figure 6. MC10H642 Negative PW versus Temperature, VCC = 5.0V
MECL Data DL122 -- Rev 6
2-5
MOTOROLA
MC10H642 MC100H642
6.2
6.0
Tpd (ns)
5.8
4.75 5.00
5.6
5.25
5.4
5.2 0 10 20 30 40 50 60 CAPACITIVE (pF)
Figure 7. MC10H642 + Tpd versus Load, VCC 5%, TA = 25C (Overshoot at 50 MHz with no load makes graph non linear)
DT
RESET, R R tpw
R trec
Q0 Q2
Q1 Q7
MC10/100H642 Figure 8. Clock Phase and Reset Recovery Time After Reset Pulse
MC10/100H642
Din
Q0.Q1
Q4 & Q5
Q2
Q7
After Power Up Figure 9. Outputs Q2 Q7 will Synchronize with Pos Edges of Din & Q0 Q1
MOTOROLA
2-6
MECL Data DL122 -- Rev 6
MC10H642 MC100H642
SWITCHING CIRCUIT AND WAVEFORMS Switching Circuit PECL: PECL
USE 0.1 F CAPACITORS FOR DECOUPLING. 50 COAX PULSE GENERATOR IN DEVICE UNDER TEST
VEE
VCC & VCCO
TTL
+7 V OPEN ALL OTHERS tPZL, tPLZ OC DEVICE UNDER TEST 50 pF R2 500 R1 500
OUT 450 50 COAX
USE OSCILLOSCOPE INTERNAL 50 LOAD FOR TERMINATION.
CH A OSCILLOSCOPE
WAVEFORMS: Rise and Fall Times PECL/TTL
50 COAX 80%/2.0 V Vout 20%/0.8 V
CH B
Propagation Delay -- Single Ended PECL/TTL
50%/1.5 V Vin
Tpd++ 50%/1.5 V
Tpd--
Trise
Tfall
Vout
MECL Data DL122 -- Rev 6
2-7
MOTOROLA
MC10H642 MC100H642
OUTLINE DIMENSIONS
FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE D
B -N- Y BRK U D Z -L- -M- 0.007 (0.180)
M
0.007 (0.180)
M
T L-M
S
N
S S
T L-M
N
S
W
28 1
D
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
V
A Z R C
0.007 (0.180) 0.007 (0.180)
M
T L-M T L-M
S
N N
S
H
0.007 (0.180)
M
T L-M
S
N
S
M
S
S
E 0.004 (0.100) G G1 0.010 (0.250)
S
K1
J
-T- VIEW S
SEATING PLANE
K F VIEW S 0.007 (0.180)
M
T L-M
S
N
S
T L-M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
MOTOROLA
2-8
MECL Data DL122 -- Rev 6
MC10H642 MC100H642
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JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
MECL Data DL122 -- Rev 6 2-9
*MC10H642/D*
MC10H642/D MOTOROLA

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